Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-04-10
2007-04-10
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
11077331
ABSTRACT:
A method, system and computer program product for performing retiming in the presence of constraints are disclosed. The method comprises receiving an initial design containing one or more targets and one or more constraints and enumerating the one or more constraints and the one or more targets into a retiming gate set. A retiming graph is constructed from the initial design, and a retiming solution is obtained on the retiming graph. The retiming solution is normalized. One or more retiming lags from the retiming graph are propagated to the initial design, and the initial design is verified by using a constraint-satisfying analysis to determine whether the one or more targets may be hit while the one or more constraints are satisfied.
REFERENCES:
patent: 6216252 (2001-04-01), Dangelo et al.
Charles E. Leserson & James B. Saxe, “Retiming Synchronous Circuitry”, Article, 1991, vol./Issue No. Unknown, Springer-Verlag New York Inc., USA.
Andreas Kuehlman & Jason Baumgartner, “Transformation-Based Verification Using Generalized Retiming”, Article, 2001, vol./Issue Unknown, Springer-Verlag New York Inc., USA.
Baumgartner Jason Raymond
Mony Hari
Paruthi Viresh
Xu Jiazhao
Dillon & Yudell LLP
Do Thuan
International Business Machines - Corporation
Salys Casimer K.
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