Selective plating of package terminals

Details Selective plating of package terminals Selective plating of package terminals

2007-03-06

2007-03-06

Geyer, Scott B. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S674000, C257SE21295

Reexamination Certificate

active

10685171

ABSTRACT:
In one embodiment, a method including providing a semiconductor pad package having a first pad and a second pad is disclosed. A first layer comprising a first metal is deposited on the first pad using a first process. A second metal is then deposited on the first pad and the first layer using a second process. In another embodiment, the first process comprises and electroplating process, and the second process comprises a direct immersion gold (DIG) process. In a further embodiment, the first pad is a power or ground pad, and the second pad is a signal pad.

REFERENCES:
patent: 6110813 (2000-08-01), Ota et al.
patent: 6599767 (2003-07-01), Li
patent: 6709980 (2004-03-01), Gleason
patent: 6975025 (2005-12-01), LeBonheur et al.
patent: 2005/0121764 (2005-06-01), Mallik et al.

Affiliated with

Also associated with

Rating

Selective plating of package terminals does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Selective plating of package terminals, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective plating of package terminals will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3739561