Thin film memory, array, and operation method and...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S071000, C257S318000, C257S908000

Reexamination Certificate

active

10879938

ABSTRACT:
A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between first and second semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film.

REFERENCES:
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patent: 5283457 (1994-02-01), Matloubian
patent: 5578853 (1996-11-01), Hayashi et al.
patent: 5784311 (1998-07-01), Assaderaghi et al.
patent: 6111778 (2000-08-01), MacDonald et al.
patent: 0601590 (1994-06-01), None
patent: 58093370 (1983-06-01), None
Patent Abstracts of Japan, vol. 0112, No. 12 (E-522), publication No. 62035559, publication date Feb. 19, 1987.
Patent Abstracts of Japan, vol. 0071, No. 90 (E-164), publication No. 58093370, publication date Jun. 3, 1983.

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