Gate layouts for transistors

Details Gate layouts for transistors Gate layouts for transistors

2007-09-04

2007-09-04

Nguyen, Cuong (Department: 2811)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S128000, C438S197000

Reexamination Certificate

active

11311995

ABSTRACT:
A transistor and a method of fabricating the transistor are provided. The transistor includes a semiconductor material comprising drain regions and source regions formed in alternating rows or columns. The transistor also includes polysilicon chains overlaying the top of the semiconductor material, disconnected from and substantially parallel to one another, and separating the drain regions from the source regions. The method includes providing a semiconductor material, growing a first insulating layer on top of the semiconductor material, depositing a polysilicon layer on top of the first insulating layer, defining a plurality of chains in the polysilicon layer, the plurality of chains being disconnected from and substantially parallel to one another, and forming a plurality of drain regions and a plurality of source regions in the semiconductor material in alternating rows or columns. The plurality of chains separates the plurality of drain regions from the plurality of source regions.

REFERENCES:
patent: 6867083 (2005-03-01), Imam et al.
patent: 7064051 (2006-06-01), Lee et al.
patent: 7094674 (2006-08-01), Graf et al.
patent: 7192857 (2007-03-01), Hopper et al.
patent: 7211478 (2007-05-01), Pelham et al.

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