Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-03-20
2007-03-20
Soward, Ida M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S327000, C257S338000, C257S350000, C257S351000, C257S357000, C257S369000, C257S371000, C257S510000
Reexamination Certificate
active
10498377
ABSTRACT:
While using conventional manufacturing processes, it is intended to apply a compressive strain in the channel direction to the p-channel MOS field effect transistor and also apply a tensile strain in the channel direction to the n-channel MOS field effect transistor for increasing both MOS currents. In the MOS semiconductor device isolated by a trench device isolation regions, the p-channel MOS field effect transistor is designed so that a length of a source/drain region in the channel direction is not more than 1 micrometer, and the gate length is not more than 0.2 micrometers. The n-channel MOS field effect transistor is designed so that a face of the source/drain region in parallel to the gate width direction is adjacent to the device isolation film with the inserted silicon nitride film, and a face of the source/drain region parallel to the gate length direction is adjacent to the device isolation film including the silicon oxide film only.
REFERENCES:
patent: 5006913 (1991-04-01), Sugahara et al.
patent: 5683934 (1997-11-01), Candelaria
patent: 5852310 (1998-12-01), Kadosh et al.
patent: 6010948 (2000-01-01), Yu et al.
patent: 6211064 (2001-04-01), Lee
patent: 6310367 (2001-10-01), Yagishita et al.
patent: 6756262 (2004-06-01), Nakamura et al.
patent: 2001/0003364 (2001-06-01), Sugawara et al.
patent: 2001/0023133 (2001-09-01), Hoke et al.
patent: 2001/0023134 (2001-09-01), Akatsu et al.
patent: 2002/0048972 (2002-04-01), Yamaguchi et al.
patent: 2004/0029323 (2004-02-01), Shimizu et al.
patent: 2004/0075148 (2004-04-01), Kumagai et al.
patent: 2004/0084735 (2004-05-01), Murthy et al.
patent: 2005/0077511 (2005-04-01), Fitzergald
patent: 0 967 636 (1999-12-01), None
patent: 11-54756 (1999-02-01), None
patent: 2000-36567 (2000-02-01), None
patent: 2001-28341 (2001-01-01), None
A. Shimizu, “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement”, International Electron devices Meeting 2001, IEDM Technical Digest, Dec. 2, 2001, pp. 433-436.
G. Scott et al., “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress”, International electron Devices Meeting 1999, IEDM Technical Digest, 1999, pp. 827-830.
International Search Report dated Mar. 25, 2003.
Ono Haruihiko
Toda Akio
McGinn IP Law Group PLLC
NEC Corporation
Soward Ida M.
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