Bus arbitration in low power system

Details Bus arbitration in low power system Bus arbitration in low power system

2007-03-06

2007-03-06

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

C710S241000, C710S309000

Reexamination Certificate

active

10376816

ABSTRACT:
Power is conserved in a data processing system that includes a processor core and system circuitry coupled to the processor core. A first method for conserving power includes entering a low power state by the processor and the system circuitry and enabling bus arbitration by the processor while the processor core remains in the low power state. One embodiment further contemplates a method of conserving power by granting bus access to a requesting device and entering a power conservation mode by the processor core in response thereto. Bus operations are then performed while the processor core remains in the power conservation mode. Another embodiment contemplates a method of debugging a data processing system in which a debug state is entered by the processor and the system circuitry and, thereafter, bus arbitration is enabled by the processor while the processor core remains in the debug state.

REFERENCES:
patent: 5455912 (1995-10-01), Ludwig
patent: 5590341 (1996-12-01), Matter
patent: 5652895 (1997-07-01), Poisner
patent: 5677849 (1997-10-01), Smith
patent: 5898879 (1999-04-01), Kim
patent: 6161186 (2000-12-01), Smith
patent: 6175913 (2001-01-01), Chesters et al.
patent: 6243817 (2001-06-01), Melo et al.
PCT/US00/24605 PCT International Search Report mailed Feb. 13, 2001.

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