Semiconductor device with a non-erasable memory and/or a...

Static information storage and retrieval – Systems using particular element – Resistive

Reexamination Certificate

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Details

Other Related Categories

C365S185240, C365S189011

Type

Reexamination Certificate

Status

active

Patent number

11057682

Description

ABSTRACT:
A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.

REFERENCES:
patent: 6549455 (2003-04-01), Yamada
patent: 6707712 (2004-03-01), Lowery
patent: 6937505 (2005-08-01), Morikawa
patent: 7064970 (2006-06-01), Nazarian
patent: 2003-100084 (2003-04-01), None
A. Pirovano et al., “Electronic Switching Effect in Phase-Change Memory Cells”, 2002 IEEE, 4 pages.
Manzur Gill et al., “Ovonic Unified Memory—A High-Performance Nonvolatile Memory Technology for Stand-Alone Memory and Embedded Applications”, 2002 IEEE International Solid-State Circuits Conference, 2 pages.
Y. N. Hwang et al., “Completely CMOS-Compatible Phase-Change Nonvolatile RAM Using NMOS Cell Transistors”, 2 pages.

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