Bus clock frequency management based on characteristics of...

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis

Reexamination Certificate

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C713S500000, C713S501000, C713S502000, C713S600000, C710S100000, C710S307000, C710S309000, C370S395210, C370S395410, C375S240000, C455S177100, C455S452200

Reexamination Certificate

active

07149913

ABSTRACT:
A frequency manager automatically selects a clock frequency for each device or bus, or for a plurality of devices or buses, in a system, based on various factors and objectives. These factors and objectives can include optimizing performance of the devices without exceeding the system's power/thermal budget. The frequency manager can then control circuits that generate and provide clock signals having the selected frequency(ies) to these devices or buses. For example, in a system that is less than fully populated with devices, embodiments of the invention can select higher clock frequencies than a fully populated system would utilize. Some embodiments of the invention select higher clock frequencies for high-bandwidth devices than for low-bandwidth devices. Other embodiments use information about application programs that will be executed by systems, such as which devices these application programs will frequently access, to select higher clock frequencies for the frequently accessed devices. Yet other embodiments use information about whether the application programs are more memory or I/O intensive to allocate higher clock frequencies to either memory subsystems or I/O subsystems.

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