Memory control apparatus executing prefetch instruction

Details Memory control apparatus executing prefetch instruction Memory control apparatus executing prefetch instruction

2006-12-12

2006-12-12

Bragdon, Reginald (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

07149850

ABSTRACT:
A memory controller reads data from DRAM at a request from a plurality of masters. It includes a prefetch buffer for storing a result of a pre-reading operation, and a register for setting a specific master among a plurality of masters. When a master requests a read, the memory controller pre-reads data subsequent to the requested data, and determines whether or not the master is a specific master set by the register. If the master is the specific master set by the register, then the result of the pre-read is stored in the prefetch buffer. Thus, the prefetch buffer can effectively function in a system having a plurality of masters.

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