Method and apparatus for dynamically connecting modules in a...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

07124391

ABSTRACT:
Method and apparatus for dynamically connecting modules within a programmable logic device is described. In an example, a programmable logic device is programmed with modular circuits. A bitstream is obtained from a database. The bitstream includes a first portion associated with a module and a second portion associated with an interface to the module. The bitstream is then modified with configuration data to connect the interface to one or more of the modular logic circuits. The programmable logic device is then configured using the modified bitstream.

REFERENCES:
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patent: 6823283 (2004-11-01), Steger et al.
patent: 6920627 (2005-07-01), Blodget et al.
Xilinx, Inc.; Virtex-II Platform FPGA Handbook; Dec. 6, 2001; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 46-53.
Xilinx, Inc.; XAPP151 (v.15); “Virtex Series Configuration Architecture User Guide”; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; Sep. 27, 2000; pp. 1-45.
Xilinx, Inc.; XAPP138 (v2.5); “Virtex FPGA Series Configuration and Readback”; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California, 95124; Nov. 5, 2001; pp. 1-39.
Davin Lim and Mike Peattie; XAPP290 (1.0); “Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations”; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California, 95124; May 17, 2002; pp. 1-23.
U.S. Appl. No. 10/013,764, filed Dec. 10, 2001, Patterson.

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