Synchronization techniques in a multithreaded environment

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique

Reexamination Certificate

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C711S210000, C710S260000, C710S266000, C712S244000

Reexamination Certificate

active

07117330

ABSTRACT:
Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in a word, demand evaluation of values, parallel access of multiple threads to a list, synchronized and unsynchronized access to a data buffer, use of forwarding to avoid checking for an end of a buffer, use of sentinel word to detect access past a data structure, concurrent access to a word of memory using different synchronization access modes, and use of trapping to detect access to restricted memory.

REFERENCES:
patent: 4819234 (1989-04-01), Huber
patent: 4860285 (1989-08-01), Miller et al.
patent: 4872167 (1989-10-01), Maezawa et al.
patent: 5168554 (1992-12-01), Luke
patent: 5301325 (1994-04-01), Benson
patent: 5333280 (1994-07-01), Ishikawa et al.
patent: 5450575 (1995-09-01), Sites
patent: 5504932 (1996-04-01), Vassiliadis et al.
patent: 5533192 (1996-07-01), Hawley et al.
patent: 5542058 (1996-07-01), Brown, III et al.
patent: 5557761 (1996-09-01), Chan
patent: 5560029 (1996-09-01), Papadopoulos et al.
patent: 5564051 (1996-10-01), Halliwell et al.
patent: 5581764 (1996-12-01), Fitzgerald
patent: 5594864 (1997-01-01), Trauben
patent: 5598560 (1997-01-01), Benson
patent: 5600837 (1997-02-01), Artieri
patent: 5632032 (1997-05-01), Ault et al.
patent: 5652889 (1997-07-01), Sites
patent: 5712996 (1998-01-01), Schepers
patent: 5754855 (1998-05-01), Miller et al.
patent: 5768591 (1998-06-01), Robinson
patent: 5768592 (1998-06-01), Chang
patent: 5774721 (1998-06-01), Robinson
patent: 5787245 (1998-07-01), You et al.
patent: 5805878 (1998-09-01), Rahman et al.
patent: 5805892 (1998-09-01), Nakajima
patent: 5812811 (1998-09-01), Dubey et al.
patent: 5826265 (1998-10-01), Van Huben et al.
patent: 5867643 (1999-02-01), Sutton
patent: 5877766 (1999-03-01), Bates et al.
patent: 5881264 (1999-03-01), Kurosawa
patent: 5887166 (1999-03-01), Mallick et al.
patent: 5901315 (1999-05-01), Edwards et al.
patent: 5903730 (1999-05-01), Asai et al.
patent: 5913925 (1999-06-01), Kahle et al.
patent: 5926227 (1999-07-01), Schoner et al.
patent: 5931926 (1999-08-01), Yeung et al.
patent: 5953530 (1999-09-01), Rishi et al.
patent: 5961639 (1999-10-01), Mallick et al.
patent: 5966539 (1999-10-01), Srivastava
patent: 5974483 (1999-10-01), Ray et al.
patent: 5978902 (1999-11-01), Mann
patent: 6002872 (1999-12-01), Alexander, III et al.
patent: 6002879 (1999-12-01), Radigan et al.
patent: 6009269 (1999-12-01), Burrows et al.
patent: 6029005 (2000-02-01), Radigan
patent: 6049671 (2000-04-01), Slivka et al.
patent: 6058493 (2000-05-01), Talley
patent: 6059840 (2000-05-01), Click, Jr.
patent: 6072952 (2000-06-01), Janakiraman
patent: 6094716 (2000-07-01), Witt
patent: 6101524 (2000-08-01), Choi et al.
patent: 6112293 (2000-08-01), Witt
patent: 6151701 (2000-11-01), Humphreys et al.
patent: 6151704 (2000-11-01), Radigan
patent: 6154796 (2000-11-01), Kuo et al.
patent: 6161160 (2000-12-01), Niu et al.
patent: 6182195 (2001-01-01), Laudon et al.
patent: 6263410 (2001-07-01), Kao et al.
patent: 6473818 (2002-10-01), Niu et al.
patent: 19710252 (1998-02-01), None
patent: 0422945 (1991-04-01), None
patent: 0537098 (1993-04-01), None
patent: 0855648 (1998-07-01), None
patent: 0864979 (1998-09-01), None
patent: 0455966 (1999-11-01), None
patent: 2307760 (1997-06-01), None
“Method of Tracing Events in Multi-Threaded OS/2 Applications,” IBM Tech. Disclosure Bulletin, Sep. 1993, pp. 19-22.
Adelberg, Brad et al., “The Strip Rule System for Efficiently Maintaining Derived Data,” Sigmond Record, Association for Computing Machinery, New York, vol. 26, No. 2, Jun. 1, 1997.
Agrawal, Gagan et al., “Interprocedural Data Flow Based Optimizations for Compilation of Irregular Problems,” Annual Workshop on Languages and Compilers for Parallel Computing, 1995.
Agrawal, Hiralal, “Dominators, Super Blocks and Program Coverage, ” 21st ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, Portland, Oregon, Jan. 17-21, 1994.
Alverson, Gail et al., “Processor Management in the Tera MTA System,” 1995.
Alverson, Gail et al., “Scheduling on the Tera MTA,” Job Scheduling Strategies for Parallel Processing, 1995.
Alverson, Gail et al., “Tera Hardware-Software Cooperation,” Proceedings of Supercomputing 1997, San Jose, California, Nov. 1997.
Alverson, Robert et al, “The Tera Computer System,” Proceedings of 1990 ACM International Conference on Supercomputing, Jun. 1990.
Anderson, Jennifer, et al., “Continuous Profiling: Where Have All The Cycles Gone?,” Operating Systems Review, ACM Headquarters, New York, vol. 31, NO. 5, Dec. 1, 1997.
Bailey, D.H. et al., “The NAS Parallel Benchmarks—Summary and Preliminary Results,” Numerical Aerodynamic Simulation (NAS) Systems Divison, NASA Ames Research Center, California, 1991.
Briggs, Preston et al., “Coloring Heuristics for Register Allocation,” Department of Computer Science, Rice University, Houston, Texas, Jun. 1989.
Briggs, Preston et al., “Coloring Register Pairs,” ACM Letters on Programming Languages and Systems, vol. 1, No. 1, Mar. 1992, pp. 3-13.
Briggs, Preston et al., “Effective Partial Redundancy Elimination,” ACM SIGPLAN Notices, Association for Computing Machinery, New York, vol. 29, No. 6, Jun. 1, 1994.
Callahan, David et al., A Future-Based Parallel Language for a General -Purpose Highly-Parallel Computer, Languages and Compilers for Parallel Computing, MIT Press, 1990.
Callahan, David et al., “Improving Register Allocation for Subscripted Variables,” Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, White Plains, New York, Jun. 20-22, 1990.
Callahan, David et al., “Register Allocation via Hierarchical Graph Coloring,” Proceedings of the ACM SIGPLAN '91 Conference on Programming Language Design and Implementation, Toronto, Canada, Jun. 26, 28-1991.
Callahan, David, “Recognizing and Parallelizing Bounded Recurrences,” Aug. 1991.
Chaudhuri, Surajit et al., “An Overview of Data Warehousing and OLAP Technology,” Sigmod Record, Association for Computing, New York, vol. 26, No. 1, Mar. 1997.
Chow, Fred C. et al., “The Priority-Based Coloring Approach to Register Allocation,” ACM Transactions on Programming Languages and Systems, vol. 12, No. 4, Oct. 1990, pp. 501-536.
Click, Cliff, “Global Code Motion, Global Value Numbering,” ACM SIGPLAN Notices, Association for Computing Machinery, New York, vol. 30, No. 6, Jun. 1, 1995.
Cook, Jonathan E. et al., “Event Based Detection of Concurrency,” SIGSOFT '98 ACM, 1998, pp.34-45.
Davidson, Jack W. et al., Reducing the Cost of Branches by Using Registers, “Proceedings of the 17th Annual Symposium on Computer Architecture,” Seattle, Washington, May 28-31, 1990.
Galarowicz, Jim et al., “Analyzing Message Passing Programs on the Cray T3E with PAT and VAMPIR,” Research Report, “Online!”, May 1998.
George, Lal et al., “Iterated Register Coalescing,” ACM Transactions on Programming Languages and Systems, vol. 18, No. 3, May 1996, pp. 300-324.
Goldman, Kenneth J., “Introduction to Data Structures,” 1996 (retrieved from Internet, http://www.cs.wustl.edu{kjg/CS101—SP97/Notes?Data Structures/structures.html.
Hayashi, H. et al., “ALPHA: A High Performance Lisp Machine Equipped with a New Stack Structure and Garbage Collection System,” 10th Annual International Symposium on Computer Architecture, 1983.
Ji, Minwen et al., “Performance Measurements for Multithreaded Programs,” SIGMETRICS '98 , ACM, 1998, pp. 168-170.
Knoop, Jens et al., “The Power of Assignment Motion,” ACM SIGPLAN '95 Conference on Programming Language Desig

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