Multi-level (4state/2-bit) stacked gate flash memory cell

Details Multi-level (4state/2-bit) stacked gate flash memory cell Multi-level (4state/2-bit) stacked gate flash memory cell

2006-10-17

2006-10-17

Soward, Ida M. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S317000, C257S318000, C257S319000, C257S320000, C257S321000, C257S322000, C257S323000

Reexamination Certificate

active

07122857

ABSTRACT:
A method is provided for forming a highly dense stacked gate flash memory cell with a structure having multi floating gates that can assume 4 states and, therefore, store 2 bits at the same time. This is accomplished by providing a semiconductor substrate having gate oxide formed thereon, and shallow trench isolation and a p-well formed therein. A layer of nitride is next formed over the substrate and an opening formed therein. Polysilicon floating gate spacers are formed in the opening. A dielectric layer is then formed over the floating gates followed by the forming of a control gate. The adjacent nitride layer is then removed leaving a multi-level structure comprising a control gate therebetween multi floating gates with the intervening dielectric layer.

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