Shadow register to enhance lock acquisition

Details Shadow register to enhance lock acquisition Shadow register to enhance lock acquisition

2006-08-08

2006-08-08

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S152000

Reexamination Certificate

active

07089373

ABSTRACT:
A method and an apparatus are provided for enhancing lock acquisition in a multiprocessor system. A lock-load instruction is sent from a first processor to a cache. In response, a reservation flag for the first processor is set, and lock data is sent to the first processor. The lock data is placed in target and shadow registers of the first processor. Upon a determination that the lock is taken, the lock-load instruction is resent from the first processor to the cache. Upon a determination that the reservation flag is still set for the first processor, a status-quo signal is sent to the first processor without resending the lock data to the first processor. In response, the lock data is copied from the shadow register to the target register.

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