Strained silicon fin structure

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S328000, C257S190000, C257SE29274, C257SE29193, C257SE29262, C257SE29131, C438S156000, C438S212000

Reexamination Certificate

active

07115945

ABSTRACT:
Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

REFERENCES:
patent: 6475869 (2002-11-01), Yu
patent: 6855990 (2005-02-01), Yeo et al.
patent: 6897527 (2005-05-01), Dakshina-Murthy et al.
patent: 6977413 (2005-12-01), Hofmann et al.
patent: 2004/0061178 (2004-04-01), Lin et al.
patent: 2005/0199950 (2005-09-01), Chau et al.
patent: 2005/0202604 (2005-09-01), Cheng et al.
patent: 2005/0280103 (2005-12-01), Langdo et al.

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