Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-08-15
2006-08-15
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S133000, C711S135000, C711S136000, C711S159000, C711S160000
Reexamination Certificate
active
07093072
ABSTRACT:
Write transactions with large amounts of data using a typical cache may consume over half of the available backing store bandwidth because of the way traditional caching algorithms fill lines during a write-invoked eviction. Relaxing the traditional constraint of cache coherency improves write performance by eliminating unneeded cache line fills. This technique conserves backing store bandwidth during many write operations while having negligible impact on the cache's read performance.
REFERENCES:
patent: 5778430 (1998-07-01), Ish et al.
patent: 5895485 (1999-04-01), Loechel et al.
patent: 6041396 (2000-03-01), Widigen et al.
patent: 6574709 (2003-06-01), Skazinski et al.
patent: 6633299 (2003-10-01), Sreenivas et al.
patent: 6732234 (2004-05-01), Rowlands et al.
patent: 6748492 (2004-06-01), Rowlands et al.
patent: 6782452 (2004-08-01), Williams, III
patent: 1 074 916 (2002-02-01), None
Enterasys Networks Inc.
Lowrie Lando & Anastasi, LLP
Padmanabhan Mano
Song Jasmine
LandOfFree
Methods for improved data caching does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods for improved data caching, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for improved data caching will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3707006