Microcomputer using a shared counter

Details Microcomputer using a shared counter Microcomputer using a shared counter

2006-12-12

2006-12-12

Butler, Dennis M. (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Counting, scheduling, or event timing

C713S320000

Reexamination Certificate

active

07149915

ABSTRACT:
In a microcomputer, a watch-dog timer and a sleep control timer share a counter in their signal generating circuits. In a normal operation mode, an AND gate is in a signal passing state and a reset signal RST can be outputted. In a sleep mode, another AND gate is in a signal passing state and a wake-up signal WKUP can be outputted.

REFERENCES:
patent: 6385637 (2002-05-01), Peters et al.
patent: 6732287 (2004-05-01), Siorek et al.
patent: 6996732 (2006-02-01), Kotlow et al.
patent: 2004/0122565 (2004-06-01), Sakurai et al.
patent: A-H09-6489 (1997-01-01), None
patent: A-2001-5695 (2001-01-01), None

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