Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2006-02-07
2006-02-07
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S108000, C438S125000
Reexamination Certificate
active
06995037
ABSTRACT:
A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to provide electrical ground potential, and having a plurality of electrically insulated openings for outside electrical contacts. An outermost insulating film protecting the exposed surface of said ground layer, said film having a plurality of openings filled with metal suitable for solder ball attachment. Said second surface having the other of said metal layers attached, portions thereof being configured as a plurality of electrical signal lines, further portions as a plurality of first electrical power lines, and further portions as a plurality of second electrical power lines, selected signal and power lines being in contact with said vias. Said signal lines being distributed relative to said first power lines such that the inductive coupling between them reaches at least a minimum value, providing high mutual inductances and minimized effective self-inductance. Said signal lines further being electromagnetically coupled to said ground metal such that cross talk between signal lines is minimized. And an outermost insulating film protecting the exposed surfaces of said signal and power lines, said film having a plurality of openings filled with metal suitable for contacting selected signal and power lines and chip solder bumps.
REFERENCES:
patent: 4617586 (1986-10-01), Cuvilliers et al.
patent: 5055704 (1991-10-01), Link et al.
patent: 5710071 (1998-01-01), Beddingfield et al.
patent: 5864470 (1999-01-01), Shim et al.
patent: 5866942 (1999-02-01), Suzuki et al.
patent: 6104093 (2000-08-01), Caletka et al.
patent: 6160705 (2000-12-01), Stearns et al.
patent: 6228681 (2001-05-01), Gilleo et al.
patent: 6259587 (2001-07-01), Sheldon et al.
patent: 6396136 (2002-05-01), Kalidas et al.
patent: 6407432 (2002-06-01), Nemoto et al.
Kalidas Navinchandra
Lamson Michael A.
Brady III Wade James
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Trinh Michael
Tung Yingsheng
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