Priority encoder circuit for content addressable memory...

Details Priority encoder circuit for content addressable memory... Priority encoder circuit for content addressable memory...

2006-02-14

2006-02-14

Bataille, Pierre Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S049130, C365S189070, C706S050000

Reexamination Certificate

active

07000066

ABSTRACT:
A priority encoder circuit (300) for a content addressable memory (CAM) device is disclosed that may include a priority selection circuit (310) that receives match results (M0to Mz) and provides prioritized match results (P0to Pz), and a logic section (350) that logically combines prioritized match results (P0to Pz) to generate a smaller number of encoder inputs (RWL0to RWLr). A logic section (350) can also generate a first portion (ID0) of an encoded value (ID0to IDX). Encoder entries (314-0to314-r) may each generate a second portion (ID1to IDX) of an encoded value (ID0to IDX).

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