Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2006-02-14
2006-02-14
Auve, Glenn A. (Department: 2111)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S323000, C713S324000, C713S601000, C710S107000, C710S113000
Reexamination Certificate
active
07000131
ABSTRACT:
The present invention is generally directed to an apparatus and method for reducing excess power consumption of a bus master circuit component for use in a multi-bus master system. In one embodiment, the bus master is provided in the form of an integrated circuit comprising clock control logic that is configured to disable a clock signal that is otherwise delivered to functional circuitry contained within the integrated circuit during a period of time between the request for mastership of a bus and the grant of that request.
REFERENCES:
patent: 5652895 (1997-07-01), Poisner
patent: 6163848 (2000-12-01), Gephardt et al.
patent: 6560712 (2003-05-01), Arends et al.
patent: 2003/0172310 (2003-09-01), Moyer et al.
Duncan Richard L.
Miller William V.
Auve Glenn A.
Thomas Kayden Horstemeyer & Risley
Via Technologies Inc.
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