Methods and structures for providing programmable width and...

Details Methods and structures for providing programmable width and... Methods and structures for providing programmable width and...

2006-11-28

2006-11-28

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S758000, C365S200000, C365S020000, C360S026000, C360S047000

Reexamination Certificate

active

07143332

ABSTRACT:
A random access memory (RAM) in a programmable logic device (PLD) supports error correction as well as a configurable data width. The number of bits in a user data word varies by the selected configuration of the RAM, while the number of bits in the error correction code (ECC) is unvarying, and is based on the total width of the memory. In some embodiments, separate ports are provided for the user data and the ECC data. Thus, ECC data can be written to an ECC portion of the RAM array at a given RAM address, while at the same time user data is written to or read from a configurable user data portion of the RAM array at the same RAM address. In other embodiments, a single memory access port is used for both user data and ECC data.

REFERENCES:
patent: 6167491 (2000-12-01), McAlpine
patent: 6253299 (2001-06-01), Smith et al.
patent: 6662334 (2003-12-01), Stenfort
patent: 6941505 (2005-09-01), Yada et al.
Xilinx, Inc.; “Virtex-II Pro Platform FPGA Handbook”; published Oct. 14, 2002; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 19-71.

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