Method, apparatus, and system for improving memory access speed

Details Method, apparatus, and system for improving memory access speed Method, apparatus, and system for improving memory access speed

2006-12-05

2006-12-05

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S154000, C711S218000

Reexamination Certificate

active

07146469

ABSTRACT:
According to one embodiment of the invention, an apparatus comprises a high speed memory unit, a memory controller and an external bus interface (EBIF) unit coupled to the memory controller. The EBIF unit, based on a memory request issued by a host device to read a block of data from an external memory device, (i) initiates a burst or page mode read cycle independent of whether the memory request is associated with consecutive memory accesses to the external memory device, (ii) stores the block of data read in the high speed memory unit in response to the burse or page mode read cycle, and (iii) retrieves requested data from the high speed memory unit in response to a subsequent, non-consecutive memory request issued by the host device for data already stored within the high speed memory unit.

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