Processing device for buffering sequential and target...

Electrical computers and digital processing systems: processing – Processing control – Branching

Reexamination Certificate

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Reexamination Certificate

active

07134004

ABSTRACT:
An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.

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patent: 6-324864 (1994-11-01), None
Lee et al., “Instruction Cache Fetch Policies for Speculative Execution,” 1995, pp. 357-367.
European Search Report dated May 24, 2005.

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