Single event upset tolerant memory cell layout

Details Single event upset tolerant memory cell layout Single event upset tolerant memory cell layout

2006-11-21

2006-11-21

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S155000, C365S156000, C365S072000

Reexamination Certificate

active

07139190

ABSTRACT:
Half cells of single-event-upset-tolerant memory cells are offset by at least two rows in a memory array. Offsetting the half cells separates them to avoid simultaneous damage to both half cells from a high-energy particle that could otherwise alter multiple nodes and corrupt the data state of the memory cell. Separating the half cells by at least two rows avoids corruption that could occur if diagonally arranged half cells were hit by a high-energy particle. In a particular embodiment, offset half cells are used at the top and bottom, respectively, of two adjacent columns of memory half cells.

REFERENCES:
patent: 5640341 (1997-06-01), Bessot et al.
patent: 5981995 (1999-11-01), Selcuk
patent: 6058041 (2000-05-01), Golke et al.
patent: 6563727 (2003-05-01), Roth et al.
patent: 2006/0133134 (2006-06-01), Doyle et al.
Velazco, R. et al., “Two CMOS Memory Cells Suitable for the Design of SEU-Tolerant VLSI Circuits,”IEEE, 1994, pp. 2229-2234, available from IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Tosaka, Y. et al., “Comprehensive Study of Soft Errors in Advanced CMOS Circuits with 90/130 nm Technology,” IEEE, 2004, pp. 38.3.1-38.3.4, available from IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Kawakami, Yikiya et al., “Investigation of Soft Error Rate Including Multi-Bit Upsets in Advanced SRAM Using Neutron Irradiation Test and 3D Mixed-Mode Device Simulation,” IEEE, 2004, pp. 38.4.1-38.4.4, available from IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.

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