High-speed segmented data bus architecture

Details High-speed segmented data bus architecture High-speed segmented data bus architecture

2006-02-07

2006-02-07

Dang, Khanh (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

Reexamination Certificate

active

06996652

ABSTRACT:
A system is provided for driving data signals in an integrated circuit device. The system includes a plurality of functional blocks, each having at least one input/output connection along one side of the integrated circuit device. A data bus comprises a plurality of electrically independent segments. Each segment of the data bus spans a respective portion of the one side of the integrated circuit device. A plurality of lines electrically couple the input/output connections of the functional blocks to the segments of the data bus. The lines are grouped into a plurality of subsets, and each subset is electrically coupled to a different segment of the data bus.

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