Simultaneous multithread processor with result data delay...

Details Simultaneous multithread processor with result data delay... Simultaneous multithread processor with result data delay...

2006-02-14

2006-02-14

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: virtual mac

Task management or control

Process scheduling

C712S218000, C712S229000

Reexamination Certificate

active

07000233

ABSTRACT:
An SMT system has a single thread mode and an SMT mode. Instructions are alternately selected from two threads every clock cycle and loaded into the IFAR in a three cycle pipeline of the IFU. If a branch predicted taken instruction is detected in the branch prediction circuit in stage three of the pipeline, then in the single thread mode a calculated address from the branch prediction circuit is loaded into the IFAR on the next clock cycle. If the instruction in the branch prediction circuit detects a branch predicted taken in the SMT mode, then the selected instruction address is loaded into the IFAR on the first clock cycle following branch predicted taken detection. The calculated target address is fed back and loaded into the IFAR in the second clock cycle following branch predicted taken detection. Feedback delay effectively switches the pipeline from three stages to four stages.

REFERENCES:
patent: 2002/0138717 (2002-09-01), Joy et al.
patent: 2003/0033509 (2003-02-01), Leibholz et al.

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