Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-10-10
2006-10-10
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07120888
ABSTRACT:
A method for determining placement of circuitry during integrated circuit design. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list, the individual net weights being valid irrespective of physical design parameters. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Initial placement of the circuitry is determined in response to the composite net weight.
REFERENCES:
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5237514 (1993-08-01), Curtin
patent: 5521837 (1996-05-01), Frankle et al.
patent: 5555188 (1996-09-01), Chakradhar
patent: 5608645 (1997-03-01), Spyrou
patent: 5663888 (1997-09-01), Chakradhar
patent: 6086631 (2000-07-01), Chaudhary et al.
patent: 6099583 (2000-08-01), Nag
patent: 6233724 (2001-05-01), LaBerge
patent: 6292926 (2001-09-01), Fukui et al.
patent: 6397170 (2002-05-01), Dean et al.
patent: 6507937 (2003-01-01), Tetelbaum
patent: 6598209 (2003-07-01), Sokolov
patent: 6601226 (2003-07-01), Hill et al.
patent: 6836753 (2004-12-01), Silve
patent: 6944840 (2005-09-01), Sasaki et al.
patent: 6952816 (2005-10-01), Gupta et al.
patent: 7000210 (2006-02-01), Wu et al.
patent: 7013445 (2006-03-01), Teig et al.
patent: 2003/0159118 (2003-08-01), Lindkvist
patent: 2004/0068708 (2004-04-01), Sivaraman et al.
patent: 2004/0068711 (2004-04-01), Gupta et al.
patent: 2004/0088671 (2004-05-01), Wu et al.
patent: 2005/0034091 (2005-02-01), Harn
patent: 2006/0010413 (2006-01-01), Curtin et al.
patent: 2002245110 (2002-08-01), None
NB82081720, “I/O Pin Assignment in a Computer”, IBM Technical Disclosure Bulletin, vol. 25, No. 3B, Aug. 1, 1982, pp. 1720-1724 (6 pages).
Chuang et al., “Timing and Area Optimization for Standard-cell VLSI Circuit Design”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, No. 3, Mar. 1995, pp. 308-320.
Xi et al., “Useful-Skew Clock Routing with Gate Sizing for Low Poer Design”, Proceedings of 33rd Design Automation Conference, Jun. 3, 1996, pp. 383-388.
Curtin James J.
Raphy Ray
Szulewski Stephen
Cantor & Colburn LLP
International Business Machines - Corporation
Kik Phallaka
LandOfFree
Method, system and storage medium for determining circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method, system and storage medium for determining circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method, system and storage medium for determining circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3689855