Electrical computers and digital processing systems: virtual mac – Virtual machine task or process management
Reexamination Certificate
2006-12-05
2006-12-05
An, Meng-Ai (Department: 2195)
Electrical computers and digital processing systems: virtual mac
Virtual machine task or process management
C717S144000, C717S148000, C717S150000, C717S153000, C717S158000, C711S006000
Reexamination Certificate
active
07146613
ABSTRACT:
A digital system and method of operation is which the digital system has a processor with a virtual machine environment for interpretively executing instructions. First, a sequence of instructions is received (404) for execution by the virtual machine. The sequence of instructions is examined (408–414) to determine if a certain type of iterative sequence is present. If the certain type of iterative sequence is present, the iterative sequence is replaced (412) with a proprietary code sequence. After the modifications are complete, the modified sequence is executed in a manner that a portion of the sequence of instructions is executed in an interpretive manner (418); and the proprietary code sequences are executed directly by acceleration circuitry (420).
REFERENCES:
patent: 4713749 (1987-12-01), Magar et al.
patent: 5740441 (1998-04-01), Yellin et al.
patent: 5748964 (1998-05-01), Gosling
patent: 5983073 (1999-11-01), Ditzik
patent: 5995754 (1999-11-01), Holzle et al.
patent: 6438573 (2002-08-01), Nilsen
patent: 6633862 (2003-10-01), Thompson
patent: 6865734 (2005-03-01), Holzle et al.
patent: 6922828 (2005-07-01), Alexander et al.
patent: 6957428 (2005-10-01), Sokolov et al.
patent: 2002/0046298 (2002-04-01), Bak et al.
patent: 2002/0129225 (2002-09-01), Lindwer
patent: 2003/0061254 (2003-03-01), Lindwer et al.
patent: 2003/0070161 (2003-04-01), Wong et al.
patent: 2004/0015916 (2004-01-01), Click et al.
patent: 2004/0015917 (2004-01-01), Click et al.
patent: WO 98 59292 (1998-12-01), None
patent: WO 01 13223 (2001-02-01), None
patent: WO 01 55844 (2001-08-01), None
Lambright, “JAVA Bytecode Optimizations”, IEEE, 1997, pp. 206-210.
Piumarta et al., “Optimizing Direct Threaded Code by Selective Inlining”, ACM, 1998, pp. 291-300.
Aletan, “An Overview of RISC Architecture”, ACM, 1992, pp. 11-20.
Levy, Markus;Java To Go: Parts 1-3, Microprocessor, vol. 15, Archive 2 (www.MPRonline.com); Feb. and Mar. 2001,.
Levy, Markus;Java To Go: Part 4 and The Finale, Microprocessor, vol. 15, Archive 6 (www.MPRonline.com); Jun. 2001,.
Hsieh, Cheng-Hsueh, et al.;Optimizing NET Compilers for Improved Java Performance, IEEE Computer, Jun. 1997, pp. 67-75.
Cramer, Timothy, et al.;Compiling Java Just in Time, IEEE Micro, May/Juen. 1997, pp. 36-43.
Silberman, G.M., et al.; An Architectural Framework for Supporting Heterogeneous Instruction-Set Architectures, Computer, IEEE Computer Society, Long Beach, CA, US, vol. 26, No. 6, Jun. 1, 1993, pp. 39-56.
Chauvel Gerard
D'Inverno Dominique
An Meng-Ai
Brady W. James
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
JAVA DSP acceleration by byte-code optimization does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with JAVA DSP acceleration by byte-code optimization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and JAVA DSP acceleration by byte-code optimization will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3683558