Memory stack architecture for reduced TLB misses

Details Memory stack architecture for reduced TLB misses Memory stack architecture for reduced TLB misses

2006-08-29

2006-08-29

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S173000, C711S152000, C711S163000, C707S793000

Reexamination Certificate

active

07100014

ABSTRACT:
One embodiment disclosed relates to a computer system. The computer system includes a microprocessor, an operating system, and a memory system. The microprocessor includes a register stack and a register stack engine (RSE), and the operating system includes a kernel. The memory system is configured to have a single memory page that includes both a kernel stack and an RSE stack. The memory system may be further configured such that the kernel stack and the RSE stack grow in opposite directions and such that a uarea data structure is located between those two stacks.

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