Clock generator for pseudo dual port memory

Details Clock generator for pseudo dual port memory Clock generator for pseudo dual port memory

2006-06-13

2006-06-13

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S189040, C365S194000

Reexamination Certificate

active

07061822

ABSTRACT:
A clock generating circuit for a pseudo dual port memory incorporates feedback, delays, and latches to ensure that the write (read) operation clock pulse is sufficiently spaced in time from the read (write) operation clock. The clock generating circuit receives an external clock, a read enable signal, a write enable signal, and a reset signal as inputs. Advantages include minimization of the clock cycle time and operation unaffected by the duty ratio of an external clock. Delay circuitry may be added such that the generated clock signal has sufficient fan out and is sufficiently stable.

REFERENCES:
patent: 5375089 (1994-12-01), Lo
patent: 5812486 (1998-09-01), Shinmori
patent: 6011730 (2000-01-01), Sample et al.
patent: 6166963 (2000-12-01), Wen
patent: 6430088 (2002-08-01), Plants et al.
patent: 6590826 (2003-07-01), Sawyer

Affiliated with

Also associated with

Rating

Clock generator for pseudo dual port memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock generator for pseudo dual port memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock generator for pseudo dual port memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3670936