Method, apparatus, and program for block-based static timing...

Details Method, apparatus, and program for block-based static timing... Method, apparatus, and program for block-based static timing...

2006-02-14

2006-02-14

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07000205

ABSTRACT:
A block-based statistical timing analysis technique is provided in which the delay and arrival times in the circuit are modeled as random variables. The arrival times are modeled as Cumulative Probability Distribution Functions (CDFs) and the gate delays are modeled as Probability Density Functions (PDFs). This leads to efficient expressions for both max and addition operations, the two key functions in both regular and statistical timing analysis. Although the proposed approach can handle any form of the CDF, the CDFs may also be modeled as piecewise linear for computational efficiency. The dependency caused by reconvergent fanout is addressed, which is a necessary first step in a statistical STA framework. Reconvergent fanouts are efficiently handled by a common mode removal approach using statistical “subtraction.”

REFERENCES:
patent: 6385759 (2002-05-01), Batarekh
patent: 6557151 (2003-04-01), Donath et al.
patent: 6629293 (2003-09-01), Chang et al.
patent: 6718529 (2004-04-01), Iwanishi

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