Passivation layer for group III-V semiconductor devices

Details Passivation layer for group III-V semiconductor devices Passivation layer for group III-V semiconductor devices

2006-02-14

2006-02-14

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Having heterojunction

Reexamination Certificate

active

06998320

ABSTRACT:
A passivation layer for a heterojunction bipolar transistor (HBT) is formed from a relatively high bandgap material that is lattice-matched to the HBT components it passivates. By selecting the passivation layer to have a higher bandgap than the HBT components, minority carriers are contained within the HBT by the passivation layer. At the same time, the lattice matching of the passivation layer ensures a robust bond that prevents the subsequent formation of dangling bonds at the exterior surfaces of the base and collector (and/or other passivated surfaces), thereby minimizing surface leakage currents.

REFERENCES:
patent: 3993506 (1976-11-01), Moon
patent: 5322573 (1994-06-01), Jain et al.
Kikawa et al.; “Passivation Of InP-Based Heterostructure Bipolar Transistors-Relation To Surface Fermi Level”, 10thIntern. Conf. on Indium Phosphide and Related Materials, May 11-15, 1998 Tsukuba, Japan.
Wang et al., “Understanding The Degradation Of InP/GaAs Heterojunction Bipolar Transistors Induced By Silicon Nitride Passivation”, 2001 International Conference on Indium Phosphide and Related Materials Conference Prodeedings 13thIPRM May 14-18, 2001 Nara, Japan.

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