Process integration of SOI FETs with active layer spacer

Details Process integration of SOI FETs with active layer spacer Process integration of SOI FETs with active layer spacer

2006-10-10

2006-10-10

Chen, Kin-Chan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S706000

Reexamination Certificate

active

07119023

ABSTRACT:
A method of manufacturing a microelectronics device including providing a substrate having an active layer, a dielectric layer and a structural layer, wherein the active layer is formed over the dielectric layer and the dielectric layer is formed over the structural layer. The method further includes forming an opening through the active layer thereby exposing a surface of the dielectric layer and defining active layer sidewalls. A spacer is formed covering a first portion of the exposed dielectric layer surface and substantially spanning one of the active layer sidewalls. At least a second portion of the exposed dielectric layer surface is then cleaned.

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