Method for forming cmos device with self-aligned contacts...

Details Method for forming cmos device with self-aligned contacts... Method for forming cmos device with self-aligned contacts...

2006-08-29

2006-08-29

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Having heterojunction

C438S320000, C438S199000

Reexamination Certificate

active

07098114

ABSTRACT:
A method for forming CMOS devices on a semiconductor substrate is disclosed in which gate structures are formed within both the core region and the non-core region of the semiconductor substrate. The gate structures include a gate dielectric layer and a gate film stack that includes a conductive layer and an overlying hard mask. The hard mask is then removed from the gate structures in the non-core region. A salicide process is then performed so as to form a silicide layer in the non-core region. A barrier layer is formed that extends over the core region and a pre-metal dielectric film is formed that extends over the barrier layer. A selective etch process is performed so as to form self-aligned contact openings that extend through the pre-metal dielectric film and through the barrier layer in the core region. These openings are then filled with conductive material to form self-aligned contacts in the core region. This produces a CMOS device in the core region that has high device density and includes high-speed CMOS devices the non-core region.

REFERENCES:
patent: 5963803 (1999-10-01), Dawson et al.
patent: 6534414 (2003-03-01), Wang et al.

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