Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-05-30
2006-05-30
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07055113
ABSTRACT:
A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.
REFERENCES:
patent: 4656592 (1987-04-01), Spaanenburg et al.
patent: 5553002 (1996-09-01), Dangelo et al.
patent: 5703788 (1997-12-01), Shei et al.
patent: 5818728 (1998-10-01), Yoeli et al.
patent: 5818729 (1998-10-01), Wang et al.
patent: 6212667 (2001-04-01), Geer et al.
patent: 6459136 (2002-10-01), Amarilio et al.
patent: 6546524 (2003-04-01), Chankramath et al.
patent: 6634008 (2003-10-01), Dole
patent: 6668360 (2003-12-01), Liu
patent: 2002/0073380 (2002-06-01), Cooke et al.
patent: 2003/0000615 (2003-01-01), Baumgartner et al.
patent: 01202397 (2001-07-01), None
patent: 02202886 (2002-07-01), None
“Flow management Requirements of a Test Harness for Testing the Reliability of an Electronic CAD System”, 1994 European Design and Test Conference, pp. 605-609.—Author(s)—G. Bartels et al.
“Mask Cycle Time and Serviceability Improvement through Capacity Planning and Scheduling Software”, 1997 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 58-61—Author(s)—M. Caron et al.
“A Data Management Interface as part of the Framework of an Integrated VLSI-Design System”, ICCAD-1989, pp. 284-287—Author(s)—E. Siepmann.
Broberg, III Robert Neal Carlton
Byrn Jonathan William
Delp Gary Scott
Eneboe Michael K.
McClannahan Gary Paul
Dinh Paul
LSI Logic Corporation
Ojanen Law Offices
Whitmore Stacy A.
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