Method of fabricating a vertically integrated memory cell

Details Method of fabricating a vertically integrated memory cell Method of fabricating a vertically integrated memory cell

2006-08-29

2006-08-29

Weiss, Howard (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S270000

Reexamination Certificate

active

07098122

ABSTRACT:
A unique cell structure for use in flash memory cell and a method of fabricating the memory cell. More particularly, a vertically integrated transistor having a pair of floating gates is fabricated within a trench in a substrate. The floating gates are fabricated using sidewall spacers within the trench. A doped region is buried at the bottom of the trench. The structure can be fabricated such that the buried doped region provides a connecting layer in a multi-bit flash memory cell. Alternatively, the buried doped region may be used as a buried bitline in a single bit flash memory cell.

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