High density plasma oxide gap filled patterned metal layers with

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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438688, 438622, H01L 2144

Patent

active

060461063

ABSTRACT:
Borderless submicron vias are formed between patterned metal layers gap filled with a high density plasma oxide. Heat treatment is conducted after chemical vapor deposition of the high density plasma oxide to substantially increase the grain size of the patterned metal layers, thereby improving electromigration resistance.

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S. Bothra et al., "Integration of 0.25.mu.m Three and Five Level Interconnect System for High Performance ASIC", Proceedings of VMIC Conference, 1997 ISMIC, Jun. 1997, pp. 43-48.

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