Enabling verification of a minimal level sensitive timing...

Details Enabling verification of a minimal level sensitive timing... Enabling verification of a minimal level sensitive timing...

2006-02-07

2006-02-07

Rodriguez, Paul L. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Timing

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06996515

ABSTRACT:
A method and a corresponding apparatus for verifying a minimal level sensitive timing abstraction model provides for an extension of the timing abstraction model. The method modifies and runs the timing abstraction model with certain stimulus to establish whether the timing results with the timing abstraction model are identical to the timing result with the modeled circuit. The timing abstraction model extension, which enables verification of the timing abstraction model, only negligibly increases the size of the timing abstraction model, thus keeping STA runtimes short and the memory requirements small.

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Albrecht et al., “Cycle Time and Slack Optimization for VLSI-chips” p. 232-238 1999 IEEE/ACM International Conference on Computer-aided Design.
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