Method for optimizing utilization of a...

Details Method for optimizing utilization of a... Method for optimizing utilization of a...

2006-08-08

2006-08-08

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S167000, C345S543000

Reexamination Certificate

active

07089369

ABSTRACT:
A predictive memory performance optimizing unit for use with an interleaved memory, for example a DDR SDRAM memory, and suitable for use in a computer graphics system, among others, is described. The unit maintains a queue of pending requests for data from the memory, and prioritizes precharging and activating interleaves with pending requests. Interleaves which are in a ready state may be accessed independently of the precharging and activation of non-ready interleaves. The unit utilizes idle cycles occurring between consecutive requests to activate interleaves with pending requests.

REFERENCES:
patent: 6725347 (2004-04-01), Yang et al.
patent: 2004/0080512 (2004-04-01), McCormack et al.

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