Planarizing sacrificial oxide to improve gate critical...

Details Planarizing sacrificial oxide to improve gate critical... Planarizing sacrificial oxide to improve gate critical...

2006-08-15

2006-08-15

Schillinger, Laura M. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S164000, C438S151000

Reexamination Certificate

active

07091068

ABSTRACT:
A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and depositing a gate material over the fin structure. The method may also include forming a sacrificial material over the gate material and planarizing the sacrificial material. An antireflective coating may be deposited on the planarized sacrificial material. A gate structure may then be formed by etching the gate material.

REFERENCES:
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6686231 (2004-02-01), Ahmed et al.
patent: 6756643 (2004-06-01), Achuthan et al.
patent: 6787439 (2004-09-01), Ahmed et al.
patent: 6800885 (2004-10-01), An et al.
patent: 6800910 (2004-10-01), Lin et al.
patent: 6803631 (2004-10-01), Dakshina-Murthy et al.
patent: 6812076 (2004-11-01), Achuthan et al.
patent: 6815268 (2004-11-01), Yu et al.
patent: 6933219 (2005-08-01), Lingunis et al.
patent: 6982464 (2006-01-01), Achuthan et al.
patent: 7001837 (2006-02-01), Ngo et al.
patent: 7029959 (2006-04-01), Yang et al.
patent: 2004/0126975 (2004-07-01), Ahmed et al.
Digh Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFet,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFet: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.

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