TFT-based common gate CMOS inverters, and computer systems...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S368000, C257S369000, C257S401000, C257S402000, C438S199000, C438S285000

Reexamination Certificate

active

06998683

ABSTRACT:
Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and PFET devices can have an active region extending into both a strained crystalline lattice and a relaxed crystalline lattice. The relaxed crystalline lattice can comprise appropriately-doped silicon/germanium. The strained crystalline lattice can comprise, for example, appropriately doped silicon, or appropriately-doped silicon/germanium. The CMOS inverter can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic).

REFERENCES:
patent: 6649480 (2003-11-01), Fitzgerald et al.
patent: 6649935 (2003-11-01), Hsu et al.
patent: 6649980 (2003-11-01), Noguchi
Ono, K. et al., “Analysis of Current-Voltage Characteristics in Polysilicon TFTs for LCDs”, IEDM Tech. Digest, 1988, pp. 256-259.
Yamauchi, N. et al., “Drastically Improved Performance in Poly-Si TFTs with Channel Dimensions Comparable to Grain Size”, IEDM Tech. Digest, 1989, pp. 353-356.
King, T. et al, “A Low-Temperature (550° C) Silicon-Germanium MOS Thin-Film Transistor Technology for Large-Area Electronics”, IEDM Tech. Digest, 1991, pp. 567-570.
Kuriyama, H. et al., “High Mobility Poly-Si TFT by a New Excimer Laser Annealing Method for Large Area Electronics”, IEDM Tech. Digest, 1991, pp. 563-566.
Jeon, J. et al., “A New Poly-Si TFT with Selectively Doped Channel Fabricated by Novel Excimer Laser Annealing”, IEDM Tech. Digest, 2000, pp. 213-216.
Kim, C.H. et al., “A New High -Performance Poly-Si TFT by Simple Excimer Laser Annealing on Selectively Floating a-Si Layer”, IEDM Tech. Digest, 2001, pp. 751-754.
Hara, A. et al, “Selective Single-Crystalline-Silicon Growth at the Pre-Defined Active Regions of TFTs on a Glass by a Scanning CW Layer Irradiation”, IEDM Tech. Digest, 2000, pp. 209-212.
Hara, A. et al., “High Performance Poly-Si TFTs on a Glass by a Stable Scanning CW Laser Lateral Crystallization”, IEDM Tech. Digest, 2001, pp. 747-750.
Jagar, S. et al., “Single Grain Thin-Film-Transistor (TFT) with SOI CMOS Performance Formed by Metal-Induced-Lateral-Crystallization”, IEDM Tech. Digest, 1999, p. 293-296.
Gu, J. et al., “High Performance Sub-100 nm Si Thin-Film Transistors by Pattern-Controlled Crystallization of Thin Channel Layer and High Temperature Annealing”, DRC Conference Digest, 2002, pp. 49-50.
Kesan, V. et al., “High Performance 0.25μm p-MOSFETs with Silicon- Germanium Channels for 300K and 77K Operation”, IEDM Tech. Digest, 1991, pp. 25-28.
Garone, P.M. et al., “Mobility Enhancement and Quantum Mechanical Modeling in GeSi Channel MOSFETs from 90 to 300K”, IEDM Tech. Digest, 1991, pp. 29-32.
Feder, B.J., “I.B.M. Finds Way to Speed Up Chips”, The New York Times, Jun. 8, 2001, reprinted from http://www.nytimes.com/2001/06/08 /technology/08BLUE.html, 2 pgs.
Rim, K. et al., “Strained Si NMOSFET's for High Performance CMOS Technology”, 2001 Sympos. on VLSI Tech. Digest of Technical Papers, p. 59-60.
Li, P. et al., “Design of High Speed SVSiGe Heterojunction Complementary MOSFETs with Reduced Short-Channel Effects”, Natl. Central University, ChungLi, Taiwan, ROC, Aug. 2001, Contract No. NSC 89-2215-E-008-049, National Science Council of Taiwan., pp. 1, 9.
Ernst, T. et al., “Fabrication of a Novel Strained SiGe:C-channel Planar 55 nm nMOSFET for High-Performance CMOS”, 2002 Sympos. on VLSI Tech. Digest of Technical Papers, pp. 92-93.
Rim, K. et al., “Characteristics and Device Design of Sub-100 nm Strained SiN- and PMOSFETs”, 2002 Sympos. on VLSI Tech. Digest of Technical Papers, pp. 98-99.
Belford, R.E. et al., “Performance-Augmented CMOS Using Back-End Uniaxial Strain”, DRC Conf. Digest, 2002, pp. 41-42.
Shima, M. et al., “<100> Channel Strained-SiGe p-MOSFET with Enhanced Hole Mobility and Lower Parasitic Resistance”, 2002 Sympos. on VLSI Tech. Digest of Technical Papers, pp. 94-95.
Nayfeh, H.M. et al., “Electron Inversion Layer Mobility in Strained-Si n-MOSFET's with High Channel Doping Concentration Achieved by Ion Implantation”, DRC Conf. Digest, 2002, pp. 43-44.
Bae, G.J. et al., “A Novel SiGe-Inserted SOI Structure for High Performance PDSOI CMOSFET”, IEDM Tech. Digest, 2000, pp. 667-670.
Cheng, Z. et al., “SiGe-on-Insulator (SGOI): Substrate Preparation and MOSFET Fabrication for Electron Mobility Evaluation” and conference outline, MIT Microsystems, Tech. Labs, Cambridge, MA, 2001 IEEE Internatl. SOI Conf., Oct. 2001, pp. 13-14, 3-pg. outline.
Huang, L.J. et al., “Carrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bonding”, 2001 Sympos. on VLSI Tech. Digest of Technical Papers, pp. 57-58.
Mizuno, T. et al., “High Performance CMOS Operation of Strained-SOI MOSFETs Using Thin Film SiGe-on-Insulator Substrate”, 2002 Sympos. on VLSI Tech. Digest of Technical Papers, p. 106-107.
Tezuka, T. et al., “High-Performance Strained Si-on-Insulator MOSFETs by Novel Fabrication Processes Utilizing Ge-Condensation Technique”, 2002 VLSI Tech. Digest of Technical Papers, pp. 96-97.
Takagi, S., “Strained-Si- and SiGe-on-Insulator (Strained SOI and SGOI) MOSFETs for High Performance/Low Power CMOS Application”, DRC Conf. Digest, 2002, pp. 37-40.
“IBM Builds World's Fastest Communications Microchip”, Reuters U.S. Company News, Feb. 25, 2002, reprinted from http://activequote300.fidelity.com/rtnews/ individual n. . . /. . . . 1 pg.
Markoff, J., “I.B.M. Circuits are Now Faster and Reduce Use of Power”, The New York Times, Feb. 25, 2002, reprinted Mar. 20, 2002 from http://story.news.yahoo.com/ news?tmpl=story&u=
yt/20020225/. . . , 1 pg.
Park, J.S. et al., “Normal Incident SiGe/Si Multiple Quantum Well Infrared Detector”, IEDM Tech. Digest, 1991, pp. 749-752.
Current, M.I. et al., “Atomic-Layer Cleaving with SiGe Strain Layers for Fabrication of Si and Ge-Rich SOI Device Layers”, 2001 IEEE Internatl. SOI Conf. Oct. 2001, pp. 11-12.
Bhattacharyya, A., “The Role of Microelectronic Integration in Environmental Control: A Perspective”, Mat. Res. Soc. Symp. Proc. vol. 344, 1994, pp. 281-293.
Myers, S.M. et al., “Deuterium Interactions in Oxygen-Implanted Copper”, J. Appl. Phys., vol. 65(1), Jan. 1, 1989, p. 311-321.
Saggio, M. et al., “Innovative Localized Lifetime Control in High-Speed IGBT's ”, IEEE Elec. Dev. Lett, V. 18, No. 7, Jul. 1997, pp. 333-335.
Lu, N.C.C. et al., “A Burled-Trench DRAM Cell Using a Self-Aligned Epitaxy Over Trench Technology”, IEDM Tech. Digest, 1988, pp. 588-591.
Yamada, T. et al., “Spread Source/Drain (SSD) MOSFET Using Selective Silicon Growth for 64Mbit DRAMs”, IEDM Tech. Digest, 1989, pp. 35-38.
van Meer, H. et al., “Ultra-Thin Film Fully-Depleted SOI CMOS with Raised G/S/D Device Architecture for Sub-100 nm Applications”, 2001 IEEE Internatl, SOI Conf, Oct. 2001, pp. 45-46.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

TFT-based common gate CMOS inverters, and computer systems... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with TFT-based common gate CMOS inverters, and computer systems..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and TFT-based common gate CMOS inverters, and computer systems... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3636950

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.