Computer system architecture and memory controller for...

Details Computer system architecture and memory controller for... Computer system architecture and memory controller for...

2006-02-21

2006-02-21

Huynh, Kim (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S023000, C710S024000, C710S026000, C710S027000, C710S028000, C700S002000, C700S003000, C700S004000, C700S005000, C700S006000

Reexamination Certificate

active

07003593

ABSTRACT:
A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port (“APIP”) added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the main microprocessor bus, are then arbitrated by the memory control circuitry forming a portion of the controller chip. In this fashion, both the microprocessors and the adaptive processors of the hybrid computing system exhibit equal memory bandwidth and latency. In addition, because it is a separate electrical port from the microprocessor bus, the APIP is not required to comply with, and participate in, all FSB protocol. This results in reduced protocol overhead which results higher yielded payload on the interface.

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