Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-02-28
2006-02-28
Smoot, Stephen W. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S389000
Reexamination Certificate
active
07005705
ABSTRACT:
It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.
REFERENCES:
patent: 5440161 (1995-08-01), Iwamatsu et al.
patent: 5559368 (1996-09-01), Hu et al.
patent: 5872383 (1999-02-01), Yagishita
patent: 6462379 (2002-10-01), Higashi et al.
patent: 6521959 (2003-02-01), Kim et al.
patent: 6620656 (2003-09-01), Min et al.
patent: 6724048 (2004-04-01), Min et al.
patent: 2001/0031518 (2001-10-01), Kim et al.
patent: 2002/0048972 (2002-04-01), Yamaguchi et al.
patent: 2003/0052347 (2003-03-01), Fung
patent: 2003/0141543 (2003-07-01), Bryant et al.
patent: 8-125187 (1996-05-01), None
patent: 2001298195 (2001-10-01), None
Imai et al., “Method and System for Fabricating MOS Type Semiconductor Device Having SOI Structure,” English translation of JP 8-125187 A, published on May 17, 1996.
Y. Hirano, et al., IEEE International SOI Conference, pp. 131-132, “Bulk-Layout-Compatible 0.18μm SOI-CMOS Technology Using Body-Fixed Partial Trench Isolation (PTI)”, Oct. 1999.
S. Maeda, et al., IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 154-155, “Impact of 0.18μm SOI CMOS Technology Using Hybrid Trench Isolation With High Resistivity Substrate on embedded RF/Analog Applications”, 2000.
Y. Hirano, et al., IEEE IEDM, pp. 467-470, “Impact Of 0.10 um SOI CMOS With Body-Tied Hybrid Trench Isolation Structure to Break Through the Scaling Crisis Of Silicon Technology”, 2000.
S. Maeda, et al., Extended Abstracts of the 2001 International Conference on Solid State Devices and Materials, pp. 270-271, “A Highly Reliable 0.18 um SOI CMOS Technology for 3.3V/1.8V Operation Using Hybrid Trench Isolation and Dual Gate Oxide”, 2001.
B. W. Min, IEEE International SOI Conference, pp. 71-72, Partial Trench Isolated Body-Tied (PTIBT) Structure for SOI Applications, 2001.
L. K. Han, et al., IEEE IEDM 97, pp. 643-646, “Electrical Characteristics and Reliability of Sub-3 nm Gate Oxides Grown on Nitrogen Implanted Silicon Substrates”, 1997.
Ipposhi Takashi
Iwamatsu Toshiaki
Maeda Shigenobu
Matsumoto Takuji
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Renesas Technology Corporation
Smoot Stephen W.
LandOfFree
MOS transistor on an SOI substrate with a body contact and a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MOS transistor on an SOI substrate with a body contact and a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS transistor on an SOI substrate with a body contact and a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3634024