Mirror image memory cell transistor pairs featuring poly...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S321000, C257S331000

Reexamination Certificate

active

07057235

ABSTRACT:
By arranging floating spacer and gate non-volatile memory transistors in symmetric pairs, increased chip density may be attained. For each pair of such transistors, the floating gates are laterally aligned with floating spacers appearing on laterally outward edges of each floating gate. At laterally inward edges, the two transistors share a common drain electrode. The transistors are independent of each other except for the shared drain electrode. Tunnel oxide separated the floating spacer from the floating gate, but both the spacer and the gate are maintained at a common potential, thereby providing dual paths for charge exiting the tunnel oxide, as the charged is propelled by a programming voltage. The pairs of transistors can be aligned in columns with the direction of the columns orthogonal to the direction of the pairs, thereby forming a memory array.

REFERENCES:
patent: 4814594 (1989-03-01), Drexler
patent: 4931847 (1990-06-01), Corda
patent: 5108939 (1992-04-01), Manley et al.
patent: 5406521 (1995-04-01), Hara
patent: 5487034 (1996-01-01), Inoue
patent: 5761126 (1998-06-01), Chi et al.
patent: 5808338 (1998-09-01), Gotou
patent: 5999456 (1999-12-01), Sali et al.
patent: 6043530 (2000-03-01), Chang
patent: 6160287 (2000-12-01), Chang
patent: 6240021 (2001-05-01), Mori
patent: 6323088 (2001-11-01), Gonzalez
patent: 6343031 (2002-01-01), Murata
patent: 6385689 (2002-05-01), Cummins et al.
patent: 6468863 (2002-10-01), Hsieh et al.
patent: 6479351 (2002-11-01), Lojek et al.
patent: 6486032 (2002-11-01), Lin et al.
patent: 6541816 (2003-04-01), Ramsbey et al.
patent: 6563733 (2003-05-01), Chang et al.
patent: 6580116 (2003-06-01), Ogura
patent: 6597047 (2003-07-01), Arai et al.
patent: 2003/0199143 (2003-10-01), Lin et al.
patent: 11186415 (1997-12-01), None
patent: 11154712 (1999-06-01), None

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