Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-02-14
2006-02-14
Anderson, Matthew D. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S145000, C711S158000
Reexamination Certificate
active
07000080
ABSTRACT:
A channel-based mechanism resolves race conditions in a computer system between a first processor writing modified data back to memory and a second processor trying to obtain a copy of the modified data. In addition to a Q0channel for carrying requests for data, a Q1channel for carrying probes in response to Q0requests, and a Q2channel for carrying responses to Q0requests, a new channel, the QWB channel, which has a higher priority than Q1but lower than Q2, is also defined. When a forwarded Read command from the second processor results in a miss at the first processor's cache, because the requested memory block was written back to memory, a Loop command is issued to memory by the first processor on the QWB virtual channel. In response to the Loop command, memory sends the written back version of the memory block to the second processor.
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Tierney Gregory E.
Van Doren Stephen R.
Anderson Matthew D.
Barton Jonathan
Hewlett--Packard Development Company, L.P.
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