Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-02-28
2006-02-28
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07007265
ABSTRACT:
A method for generating mask data that is used for a method of manufacturing semiconductor devices is provided. The semiconductor device includes wiring layers disposed in a specified pattern on a base and stress relieving layers disposed in a specified pattern over the base. The method for generating mask data comprises a step of forming resized patterns130by resizing wiring layer patterns120with a positive (+) resizing amount, a step of deleting, among the resized patterns130,resized patterns having portions that mutually overlap, and a step of forming stress relieving layer patterns having a specified width outside the resized patterns.
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Harness & Dickey & Pierce P.L.C.
Smith Matthew
Tat Binh
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