Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-08-15
2006-08-15
Bragdon, Reginald G. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S129000, C711S136000
Reexamination Certificate
active
07093075
ABSTRACT:
A system and method for reducing latency in memory systems is provided. A copy way is established in a set of a set associative cache, which is physically closer to a requesting entity than other memory positions. Likely to be accessed data is copied to the copy way for subsequent access. In this way, subsequent accesses of the most likely data have their access time reduced due to the physical proximity of the data being close to the requesting entity. Methods herein further provide ranking and rearranging blocks in the cache based on coupled local and global least recently used (LRU) algorithms to reduce latency time.
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Hu Zhigang
Reohr William Robert
Bragdon Reginald G.
Keusey, Tutunjian & & Bitetto, P.C.
Vo Thanh D.
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