Semiconductor memory device for reducing damage to...

Details Semiconductor memory device for reducing damage to... Semiconductor memory device for reducing damage to...

2006-05-23

2006-05-23

Vu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S244000

Reexamination Certificate

active

07049648

ABSTRACT:
The semiconductor memory device includes an interlevel dielectric pattern and an adhesive pattern, wherein both the interlevel dielectric and adhesive patterns include a contact hole to expose a semiconductor substrate. The adhesive pattern sufficiently adheres a lower electrode of a capacitor to the interlevel dielectric pattern, and thus prevents damage to the interlevel dielectric pattern during the formation of the capacitor. A conductive plug is disposed within the contact hole and may project higher than the top surface of the adhesive pattern. A leakage current preventive pattern is formed on top of the adhesive pattern and prevents a capacitor dielectric layer from directly contacting the plug to prevent occurrences of leakage current. A lower electrode of a capacitor electrically connected to the plug is formed on the plug.

REFERENCES:
patent: 5162248 (1992-11-01), Dennison et al.
patent: 5340763 (1994-08-01), Dennison
patent: 5518948 (1996-05-01), Walker
patent: 5904703 (1999-05-01), Gilson
patent: 6114201 (2000-09-01), Wu
patent: 6180974 (2001-01-01), Okutoh et al.
patent: 6274899 (2001-08-01), Melnick et al.
patent: 6326316 (2001-12-01), Kiyotoshi et al.

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