Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2006-02-21

2006-02-21

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S196000

Reexamination Certificate

active

07002866

ABSTRACT:
In a single intersection type (open bit line type) dynamic RAM, sub-arrays are disposed to the left and right sides of a sense amplifier column placed at the center. Each sub-array has a multiplicity of dynamic memory cells. In the subarrays located to the left and right of the sense amplifier column, bit lines in the same row constitute a complementary bit line pair. In each subarray, shielding wiring patterns that are formed parallel to, and in the same wiring layer of, these bit lines are disposed between the bit lines. All of these wiring patterns are set at a fixed potential, such as a power supply potential. Thus, interference noise between adjacent bit lines is effectively reduced.

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