Method for manufacturing a multilevel interconnection structure

Details Method for manufacturing a multilevel interconnection structure Method for manufacturing a multilevel interconnection structure

1998-03-04

2000-03-07

Utech, Benjamin L.

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

H01L 2100, H01L 213065

Patent

active

06033990&

ABSTRACT:
A method for fabricating a semiconductor device on a silicon substrate comprises the step of high-frequency plasma-treatment for through-hole before filling the through-hole with a metallic layer for connection. The plasma contains argon, oxygen and hydrogen atoms wherein the ratio of oxygen atoms to the total of the oxygen and hydrogen atoms in number is between 1/3 and 1/100. The silicon substrate is applied with a high-frequency bias voltage during the plasma treatment for acceleration of argon ion.

REFERENCES:
patent: 4582563 (1986-04-01), Hazuki et al.
patent: 5007983 (1991-04-01), Lerner et al.
patent: 5346578 (1994-09-01), Benzing et al.
patent: 5399527 (1995-03-01), Tabara
Japanese Office Action dated Aug. 17, 1999 together with cited references, Japanese wavy line material and English translation thereof, Yasuhiro Horiike and Haruo Shindo, Jul. 27, 1994, p.576.
Japanese Office Action dated Aug. 17, 1999 together with cited references, Japanese wavy line material and English translation thereof.

Affiliated with

Also associated with

Rating

Method for manufacturing a multilevel interconnection structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing a multilevel interconnection structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a multilevel interconnection structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-362673