Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-05-23
2006-05-23
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C257S508000
Reexamination Certificate
active
07051311
ABSTRACT:
The present invention provides a semiconductor circuit designing method, comprising a lower level hierarchical designing step of designing a semiconductor circuit inside a block and an upper level hierarchical designing step of designing an external wiring of the block. The above-mentioned lower level hierarchical designing step or upper level hierarchical designing step includes a shield wiring designing step of designing to provide a shield wiring on a boundary part of the block.
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Baba Katsutoshi
Sugioka Toshiaki
Tomita Katsuko
Armstrong, Kratz, Quintos Hanson & Brooks, LLP.
Garbowski Leigh M.
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